Project Frankenstein: Hardware Addendum v2

Subject: Software-Driven SMC State Translation, Direct Pad Wiring, & Activity LED Routing

This addendum details the internal MN103S processor mapping required to natively translate the drive's mechanical states into Xbox-compliant SMC signals, as well as safe external routing logic for the Drive Activity LED.

1. The Target Hardware Map (Port 2)

The Xbox SMC cable will be soldered directly to three unpopulated factory test pads on the GCC-4241N motherboard. These pads are physically tied to Port 2 on the processor and are initialized as High-Z (Inputs) by the retail firmware, making them perfectly safe to hijack as outputs.

MN103S Logical Pin	Physical Test Pad	Xbox Yellow Cable Pin	Signal Purpose
`P22` (Port 2, Bit 2)	Test Pad 1	Pin 6	`TRAY_IN` (Tray Closed)
`P23` (Port 2, Bit 3)	Test Pad 2	Pin 5	`TRAY_OUT` (Tray Open)
`P24` (Port 2, Bit 4)	Test Pad 3	Pin 7	`CD_READY` (Media Ready)

Note: Xbox Pin 4 (EJECT) will be wired directly to the Eject Button trace (MONI5) to receive the external eject command.

2. Mechanical Truth Tables

The GCC-4241N slimline mechanism uses an overlapping dual-switch topology. The translation logic must account for the mechanical transition ("popped") state to prevent Xbox SMC timing errors.

Native 4241N Tray Switch States

Tray State	Back Button (`P13`)	Front Button (`MONI7`)
Closed	Closed	Closed
Popped (Moving)	Closed	Open
Open	Open	Open

Translated Xbox SMC Logic (Active-Low)

The Xbox requires a strict 0V (LOW) signal to register an active state, and 3.3V (HIGH) for an inactive state.

Drive State	Xbox TRAY_IN (P22)	Xbox TRAY_OUT (P23)	Xbox CD_READY (P24)
Fully Closed	LOW (0V)	HIGH (3.3V)	LOW (If Latched)
Popped / Moving	HIGH (3.3V)	HIGH (3.3V)	HIGH (Unlatched)
Fully Open	HIGH (3.3V)	LOW (0V)	HIGH (3.3V)

3. State Translator Pseudocode

// --- Xbox SMC State Translator ---

// 1. TRAY CLOSED LOGIC (Test Pad 1 / P22 -> Xbox Pin 6 TRAY_IN)
If (Back_Button == CLOSED AND Front_Button == CLOSED) {
    Drive Test Pad 1 (P22) LOW         // Xbox sees 0V: "Tray is Fully Closed"
} else {
    Drive Test Pad 1 (P22) HIGH        // Xbox sees 3.3V: "Tray is Ajar/Open"
}

// 2. TRAY OPEN LOGIC (Test Pad 2 / P23 -> Xbox Pin 5 TRAY_OUT)
If (Back_Button == OPEN AND Front_Button == OPEN) {
    Drive Test Pad 2 (P23) LOW         // Xbox sees 0V: "Tray is Fully Ejected"
} else {
    Drive Test Pad 2 (P23) HIGH        // Xbox sees 3.3V: "Tray is Ajar/Closed"
}

// 3. CD_READY LATCH LOGIC (Test Pad 3 / P24 -> Xbox Pin 7 CD_READY)
If (Front_Button == OPEN) {            // The tray just "popped"
    Clear Custom_Media_Latch (Set 0)   // UNLATCH CD_READY immediately
}

If (Global_Drive_State == READY_IDLE) {
    Set Custom_Media_Latch (Set 1)     // LATCH IT: We saw a good TOC read
}

If (Custom_Media_Latch == 1) {
    Drive Test Pad 3 (P24) LOW         // Xbox sees 0V: "Media Present and Ready"
} else {
    Drive Test Pad 3 (P24) HIGH        
}

4. Activity LED Routing & IDE Mapping

For custom case modifications, users often wish to mount an external Activity LED. Attempting to solder directly to the internal processor leg is highly discouraged due to the risk of burning out the MN103S GPIO block. Instead, rely on the IDE/ATAPI standard bus signals.

Internal Logic (For Reference Only)

MN103S Pin: 237 / 223
Logical Port: P0 (Port 0)
Operation: The processor outputs a logic-level signal to the base of a surface-mount NPN transistor on the PCB, which in turn sinks current for the onboard Activity LED. Do not tap this line for an external LED.

External Wiring Guide (Recommended)

The standard 50-pin JAE connector (and its 40-pin IDE breakout) contains a dedicated, open-collector line specifically designed to safely drive external activity LEDs: /DASP (Drive Active / Slave Present).

IDE Pin: Pin 39 (Mapped internally from JAE Pin 39)
Polarity: Active-Low (0V when active, High-Z/5V when inactive)
Proper Usage: Because it is an open-collector/drain signal, it acts as a sink to ground. To wire an external case LED safely:
1. Connect a 5V source (e.g., from the Molex power connector) to the positive leg (Anode) of your custom LED.
2. Solder a current-limiting resistor (e.g., 330Ω) in series with the LED to prevent burning it out.
3. Connect the negative leg (Cathode) of the LED to IDE Pin 39 (/DASP).

Circuit Logic: When the drive reads data, the hardware ATA controller internally pulls Pin 39 to Ground (0V). Current flows from the 5V rail, through the LED, through the resistor, and sinks into Pin 39, illuminating the LED safely without stressing the MN103S processor.

5. JAE 50-Pin to IDE Adapter Modifications

Standard JAE-to-IDE adapters require two physical modifications to ensure compatibility with the Xbox SMC and the high-speed 80-wire IDE cable upgrade.

Master Configuration

Action: Bridge Pin 47 (CSEL) to Pin 45 (GND) on the JAE 50-pin interface.
Purpose: The Xbox IDE bus requires the optical drive to be permanently configured as the MASTER device. Bridging Cable Select to ground hardwires this state, bypassing the need for standard IDE cable-select negotiation.

Signal Integrity (80-Wire IDE)

Action: Tie Pin 48 to Ground.
Purpose: Generic JAE adapters often leave auxiliary grounds floating. When utilizing an 80-wire IDE cable, this floating pin can introduce crosstalk and high-frequency signal degradation. Grounding this pin prevents in-transit data corruption preventing dashboard crashes.

Volume XXVIII: Hardware Addendum v3